1. Field of the Invention
The present invention relates generally to semiconductor manufacturing and, more particularly, to a method and apparatus for pre-planarizing a substrate in order to more efficiently perform a planarization operation.
2. Description of the Related Art
During copper interconnect manufacturing, a copper layer is deposited on a seed/barrier layer using an electroplating process. Components in the electroplating solution provide for appropriate gap fill on sub-micron features. However, these sub-micron features tend to plate faster than the bulk areas and larger, i.e., greater than 1 μm, trench regions. The sub-micron regions are typically found in large memory arrays such as, for example static random access memory (SRAM), and can comprise large areas of the wafer. It should be appreciated that this causes large area regions to have additional topography that must be planarized in addition to the larger trench regions that must also be planarized.
FIG. 1 is a simplified schematic diagram illustrating a silicon substrate having a copper layer deposited thereon. Copper layer 102 is deposited on a seed/barrier layer disposed over silicon wafer 100 using an electroplating process. As mentioned above, components in the electroplating solution provide for good gap fill on submicron features, such as sub-micron trenches in regions 104a and 104b, but these features tend to plate faster than the bulk areas and trench regions 106a–d. Steps or “lumps” in the topography of the substrate, illustrated by regions 108a and 108b, result over the sub-micron trench regions. Thus, these large area regions, which step up in the topography, must be planarized along with the topography over trench regions 106a–d. Exacerbating this situation is that silicon wafer 100 is typically associated with a waviness, i.e., is not perfectly flat.
Current planarization techniques are not suited to handle the resulting topography efficiently, i.e., the techniques are sensitive to pattern density and circuit layout. More specifically, CMP processes must be tuned dependent upon the incoming wafer properties. Changes are made to the CMP process, such as changing consumables (pad and slurry) used for the CMP processing, in order to accommodate variations within lots of wafers as well as different pattern densities and circuit layouts on wafers typical of mixed-product manufacturing lines. When attempting to perform a single CMP process on the topography without changing the consumables, excessive dishing and erosion occurs over trench regions 106a–d, in order to completely remove the copper from regions 108a and 108b. Additionally, not only must the CMP process remove the excess copper in regions 108a and 108b, but the CMP process must also perform this removal in a manner that follows the contour of the substrate. Current CMP processes do not suitably deal with both of these variables. An additional shortcoming of current CMP modules is that the substrate support is incapable of aligning the surface being planarized with the surface performing the removal.
In view of the foregoing, there is a need for a method and apparatus that normalizes the surface of a substrate to be planarized in order to more efficiently perform planarization processes.